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Industrial Hardening: Coherent Goes Outdoors

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June 7, 2023

Industrial Hardening: Coherent Goes Outdoors

The global optical transceiver market is expected to double in size by 2026, and coherent…

The global optical transceiver market is expected to double in size by 2026, and coherent pluggables will play a significant role in this growth as they will constitute roughly a third of those sales. While coherent is now an established solution in data center interconnects and long haul networks, it is also expected to start gaining ground in the access networks that connect mobile base stations and their controllers to the rest of the Internet. LightCounting forecasts that by 2025, coherent modules will generate 19% of all sales revenue, in an estimated market of $827 million, for transceivers in back-, mid-, and front-haul network segments. This is an increase in market share from 6% in 2021, as operators are expected to replace some of their direct detect modules with coherent ones in the coming years.

*Figure 1: Transceiver sales revenue (in USD) forecast for coherent modules in back/mid/front-haul network segments. Source: LightCounting Access Optics Market Forecast – November 2020.*

The numbers for coherent sales will only increase in the coming decade for two main reasons. First, electronic and photonic integration are making coherent pluggables economically viable and smaller (see one of our previous article on the subject). Second, the increasing data demands require access networks to increase their capacity beyond what direct detect can deliver. However, for coherent devices to become established in access networks, they must learn to live outdoors.

Controlled vs. uncontrolled environments

Coherent devices have traditionally lived in the controlled environments of data center machine rooms or network provider equipment rooms. These rooms have active temperature control, cooling systems, filters for dust and other particulates, airlocks, and humidity control. In these rooms, pluggable transceivers operate at a relatively stable temperature of around 50ºC, and they only need to survive in ambient temperatures within the commercial temperature range (C-temp) of 0 to 70ºC.

*Figure 2: Temperature ratings required across different segments of a 5G network.*

On the other hand, access networks feature uncontrolled outdoor environments at Mother Nature’s mercy and whims. It could be at the top of an antenna, on mountain ranges, inside traffic tunnels, or in the harsh winters of Northern Europe. Deployments at higher altitudes present additional problems. The air becomes less dense, so networking equipment cooling mechanisms don’t work as efficiently, so the device cannot tolerate case temperatures as high as it does at sea level. Transceivers should operate in the industrial temperature (I-temp) range of -40 to 85ºC degrees for these environments. Optics are also available in the extended temperature (e-temp) range, which can operate as hot as I-temp devices (85ºC) but cannot get any colder than -20ºC.

*Table 1: Comparing the temperature ranges of different temperature hardening standards, including industrial and automotive/full military applications*

The initial investment has a longer-term payoff

An expensive challenge for a network operator is having a product that cannot perform reliably in the uncontrolled environments of 5G deployments. With more bandwidth and computing power moving towards the network edges, coherent transceivers must endure potentially extreme conditions in outside environments. Since i-temp transceivers are more robust, they will survive for longer, and operators will ultimately buy fewer of them compared to c-temp modules. Therefore, the initial, somewhat more expensive investment in I-temp transceivers will pay off in the long run.

In addition, the growth of Internet-of-Things (IoT) applications makes reliability even more important. A network connection drop could be disastrous in many critical and business services, such as medical and self-driving car applications.

The importance of standards

Making an I-temp transceiver means that every internal component—the integrated circuits, lasers, photodetectors—must also be I-temp compliant. EFFECT Photonics has already developed I-temp pluggable transceivers with direct detection, so we understand what standards must be followed to develop temperature-hardened coherent devices.

For example, our optical transceivers comply with the Telcordia GR-468 qualification, which describes how to test optoelectronic devices for reliability under extreme conditions. Our manufacturing facilities include capabilities for the temperature cycling and reliability testing needed to match Telcordia standards, such as temperature cycling ovens and chambers with humidity control.

*Figure 3: Examples of necessary verification tests for transceivers that will operate in harsh temperatures*

EFFECT Photonics transceivers also comply with the SFF-8472 standard that describes the Digital Diagnostics Monitoring (DDM) required for temperature-hardened transceivers to compensate for temperature fluctuations. Our proprietary NarroWave technology even allows network operators to read such device diagnostics remotely, avoiding additional truck rolls to check the devices on the field. These remote diagnostics give operators a full view of the entire network’s health from the central office.

Takeaways: going from Direct-Detect to Coherent I-temp

One of our central company objectives is to bring the highest-performing optical technologies, such as coherent detection, all the way to the network edge. However, achieving this goal doesn’t just require us to focus on the optical or electronic side but also on meeting the mechanical and temperature reliability standards required to operate coherent devices outdoors. Fortunately, EFFECT Photonics can take advantage of its previous experience and knowledge in I-temp qualification for direct-detect devices as it prepares its new coherent product line.

If you would like to download this article as a PDF, then please click here.

Tags: access networks, coherent, coherent optics, commercial temperature, fiber networks, I-temp, industrial temperature, Integrated Photonics, LightCounting, NarroWave, network operators, optical transceivers, photonic integration, Photonics, pluggables, Transceivers

How To Make a Photonic Integrated Circuit

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December 1, 2022

How To Make a Photonic Integrated Circuit

Photonics is one of the enabling technologies of the future. Light is the fastest information…

Photonics is one of the enabling technologies of the future. Light is the fastest information carrier in the universe and can transmit this information while dissipating less heat and energy than electrical signals. Thus, photonics can dramatically increase the speed, reach, and flexibility of communication networks and cope with the ever-growing demand for more data. And it will do so at a lower energy cost, decreasing the Internet’s carbon footprint. Meanwhile, fast and efficient photonic signals have massive potential for sensing and imaging applications in medical devices, automotive LIDAR, agricultural and food diagnostics, and more.

Given its importance, we want to explain how photonic integrated circuits (PICs), the devices that enable all these applications, are made.

Designing a PIC

The process of designing a PIC should translate an initial application concept into a functioning photonics chip that can be manufactured. In a short course at the OFC 2018 conference, Wim Bogaerts from Ghent University summarized the typical PIC design process in the steps we will describe below.

Figure 1 Summary of the steps in a PIC design flow process

Concept and Specifications: We first have to define what goes into the chip. A chip architect normally spends time with the customer to understand what the customer wants to achieve with the chip and all the conditions and situations where the chip will be used. After these conversations, the chip application concept becomes a concrete set of specifications that are passed on to the team that will design the internals of the chip. These specs will set the performance targets of the PIC design.
Design Function: Having defined the specs, the design team will develop a schematic circuit diagram that captures the function of the PIC. This diagram is separated into several functional blocks: some of them might already exist, and some of them might have to be built. These blocks include lasers, modulators, detectors, and other components that can manipulate light in one way or another.
Design Simulation: Making a chip costs a lot of money and time. With such risks, a fundamental element of chip design is to accurately predict the chip’s behavior after it is manufactured. The functional blocks are placed together, and their behavior is simulated using various physical models and simulation tools. The design team often uses a few different simulation approaches to reduce the risk of failure after manufacturing.
Design Layout: Now, the design team must translate the functional chip schematic into a proper design layout that can be manufactured. The layout consists of layers, component positions, and geometric shapes that represent the actual manufacturing steps. The team uses software that translates these functions into the geometric patterns to be manufactured, with human input required for the trickiest placement and geometry decisions.
Check Design Rules: Every chip fabrication facility will have its own set of manufacturing rules. In this step, the design team verifies that the layout agrees with these rules.
Verify Design Function: This is a final check to ensure that the layout actually performs as was originally intended in the original circuit schematic. The layout process usually leads to new component placement and parasitic effects that were not considered in the original circuit schematic. These tests might require the design team to revisit previous functional or layout schematic steps.

The Many Steps of Fabricating a PIC

Manufacturing semiconductor chips for photonics and electronics is one of the most complex procedures in the world. For example, back in his university days, EFFECT Photonics President Boudewijn Docter described a fabrication process with a total of 243 steps!

Yuqing Jiao, Associate Professor at the Eindhoven University of Technology (TU/e), explains the fabrication process in a few basic, simplified steps:

Grow or deposit your chip material
Print a pattern on the material
Etch the printed pattern into your material
Do some cleaning and extra surface preparation
Go back to step 1 and repeat as needed

Real life is, of course, a lot more complicated and will require cycling through these steps tens of times, leading to processes with more than 200 total steps. Let’s go through these basic steps in a bit more detail.

Figure 2 Basic steps of a semiconductor fabrication process that are repeated in a single fabrication cycle. An entire wafer manufacturing process requires tens of these cycles.

Layer Epitaxy and Deposition: Different chip elements require different semiconductor material layers. These layers can be grown on the semiconductor wafer via a process called epitaxy or deposited via other methods (which are summarized in this article).

Figure 3: Simplified example of PIC elements and the different material layers they require. Source: Smit et al. (2014)

Lithography (i.e. printing): There are a few lithography methods, but the one used for high-volume chip fabrication is projection optical lithography. The semiconductor wafer is coated with a photosensitive polymer film called a photoresist. Meanwhile, the design layout pattern is transferred to an opaque material called a mask. The optical lithography system projects the mask pattern onto the photoresist. The exposed photoresist is then developed (like photographic film) to complete the pattern printing.

Figure 4 Comparison of different optical lithography approaches. Contact and proximity printing keep the mask in contact with or close to the sample. Projection printing keeps the mask further away and is initially more expensive, but it is the technology of choice for high-volume manufacturing. Source: J. Shen, University of Waterloo PhD Thesis (2018)

Etching: Having “printed” the pattern on the photoresist, it is time to remove (or etch) parts of the semiconductor material to transfer the pattern from the resist into the wafer. There are several techniques that can be done to etch the material, which are summarized in this article.

Figure 5: Example of what a semiconductor wafer with resist (red color) on top of it looks like before and after an etching step.

Cleaning and Surface Preparation: After etching, a series of steps will clean and prepare the surface before the next cycle.
- Passivation: Adding layers of dielectric material (such a silica) to “passivate” the chip and make it more tolerant to environmental effects.
- Planarization: Making the surface flat in preparation of future lithography and etching steps.
- Metallization: Depositing metal components and films on the wafer. This might be done for future lithography and etching steps, or at the end to add electrical contacts to the chip.

Figure 6 summarizes how an InP photonic device looks after the steps of layer epitaxy, etching, dielectric deposition and planarization, and metallization.

Figure 6 Cross-section of a semiconductor wafer structure after: (a) epitaxial growth, (b) etching, (c) passivation and planarization, (d) metallization.

The Expensive Process of Testing and Packaging

Chip fabrication is a process with many sources of variability, and therefore much testing is required to make sure that the fabricated chip agrees with what was originally designed and simulated. Once that is certified and qualified, the process of packaging and assembling a device with the PIC follows.

While packaging, assembly, and testing are only a small part of the cost of electronic systems, the reverse happens with photonic systems. Researchers at the Technical University of Eindhoven (TU/e) estimate that for most Indium Phosphide (InP) photonics devices, the cost of packaging, assembly, and testing can reach around 80% of the total module cost. There are many research efforts in motion to reduce these costs, which you can learn more about in one of our previous articles.

Figure 7. Process cost breakdown of an InP PIC-based module as a percentage of the overall cost of manufacturing. Source: Latkowski et al., 2019

Especially after the first fabrication run of a new chip, there will be a few rounds of characterization, validation and revisions to make sure the chip performs up to spec. After this first round of characterization and validation, the chip must be made ready for mass production, which requires a series of reliability tests in several environmental different conditions. You can learn more about this process in our previous article on industrial hardening. For example, different applications need different certification of the temperatures in which the chip must operate in.

Temperature Standard	Temperature Range (°C)
Temperature Standard	Min	Max
Commercial (C-temp)	0	70
Extended (E-temp)	-20	85
Industrial (I-temp)	-40	85
Automotive / Full Military	-40	125

Table 1: Comparing the temperature ranges of different temperature hardening standards, including industrial and automotive/full military applications

Takeaways

The process of making photonic integrated circuits is incredibly long and complex, and the steps we described in this article are a mere simplification of the entire process. It requires tremendous amount of knowledge in chip design, fabrication, and testing from experts in different fields all around the world. EFFECT Photonics was founded by people who fabricated these chips themselves, understand the process intimately, and developed the connections and network to develop cutting-edge PICs at scale.

Tags: building blocks, c-temp, coherent, die testing, DSP, electron beam lithography, faults, I-temp, imprint lithography, InP, interfaces, optical lithography, reach, scale, wafer testing

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