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Press Releases

March 27, 2023

EFFECT Photonics Acquires Coherent Optical Digital Signal Processing Business from Viasat

EFFECT Photonics to Become the Most Highly Vertically Integrated, Independent Coherent Optical Module Vendor San…

EFFECT Photonics to Become the Most Highly Vertically Integrated, Independent Coherent Optical Module Vendor

San Diego, United States America – Today at OFC (Optical Fiber Conference) 2022, EFFECT Photonics, a leading provider of highly integrated optical communication products is announcing that it signed a definitive agreement to acquire coherent optical digital signal processing (DSP) and forward error correction (FEC) technology as well as a highly experienced engineering team from global communications company, Viasat Inc. (NASDAQ: VSAT).

Viasat is a long-established player in DSP and FEC technology. With eight generations of design IP, they have a proven track record of delivering successful field deployments.

From this acquisition, EFFECT Photonics will now own the entire coherent technology stack of all optical functions, including a high-performance tunable laser, together with DSP and FEC. This will enable the Company to deliver on its ambition to make high performance coherent communications solutions widely accessible and affordable. Furthermore, it will enable longer term economic and environmentally sustainable communications due to the ability to deliver high-end performance and reach within a small footprint and with lower power consumption. This opens the way to drive coherent technology into new places, revolutionizing the way the world interconnects.

This transaction is expected to provide the following customer benefits:

EFFECT Photonics will be able to optimize the complete solution for any application addressing both existing challenges and new possibilities
With full ownership of the key optical, DSP and FEC functions, EFFECT Photonics can offer seamless integration, cost efficiency and security of supply
EFFECT Photonics will be an independent vendor able to offer a full portfolio of building blocks such as the tunable laser and DSP, and/or complete solutions, increasing the choice reduced by recent mergers and acquisitions in the industry

EFFECT Photonics has also secured an additional $20M in Series-C funding bringing the total to $63M. Additionally, pursuant to the DSP acquisition agreement, Viasat will be joining EFFECT Photonics’ Supervisory Board and hold a minority interest in the Company.

“This is a significant step in accelerating our ambition to make coherent optical communications ubiquitous and further drive our product portfolio growth. We look forward to welcoming the team of highly skilled and experienced design architects and engineers who will be joining us to drive the development of energy efficient, high performance and affordable coherent solutions.

With all the recent changes in the industry landscape, this means that EFFECT Photonics is the only independent vendor able to deliver both the active optical components and the DSP. This will offer the market more choice and the ability to source superior solutions“
James Regan, CEO EFFECT Photonics.

“Given the trend of the fiber optic communications industry towards consolidation to provide vertically integrated end-to-end solutions, we believe that combining Viasat’s assets and capabilities with the unique integrated photonics capabilities of EFFECT Photonics will create substantially more market opportunities and better products. By investing in this Netherlands-headquartered company, we will also further expand our presence in Europe and be able to partner with EFFECT to bring state-of-the-art integrated photonics to Viasat’s own customers.”
Russell Fuerst, business area leader and vice president, Viasat.

–End of press release–

About EFFECT Photonics

EFFECT Photonics delivers highly integrated optical communications products based on its Dense Wavelength Division Multiplexing (DWDM) optical System-on-Chip technology. The key enabling technology for DWDM systems is full monolithic integration of all photonic components within a single chip and being able to produce these in volume with high yield at low cost. With this capability, EFFECT Photonics is addressing the need for affordable DWDM solutions driven by the soaring demand for high bandwidth connections. EFFECT Photonics is headquartered in The Netherlands, with additional facilities in the UK, the US and Taiwan, and a worldwide network of sales partners. https://old.effect.jkc-dev.nl

About Viasat

Viasat is a global communications company that believes everyone and everything in the world can be connected. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the world communicate. Today, the Company is developing the ultimate global communications network to power high-quality, secure, affordable, fast connections to impact people’s lives anywhere they are—on the ground, in the air or at sea. To learn more about Viasat, visit: www.viasat.com, go to Viasat’s Corporate Blog, or follow the Company on social media at: Facebook, Instagram, LinkedIn, Twitter or YouTube.

Copyright © 2022 EFFECT Photonics. All rights reserved. Viasat, the Viasat logo and the Viasat signal are registered trademarks of Viasat, Inc. All other product or company names mentioned are used for identification purposes only and may be trademarks of their respective owners.

Tags: acquisition, coherent, coherent communication systems, coherent optical module vendor, DSP, FEC, forward error correction, high vertical integration, independent coherent optical module vendor, Integrated Photonics, optical digital signal processing, optical engine, tunable laser, Viasat

07 March 2023 - 09 March 2023

8:00 am - 5:00 pm

EFFECT Photonics #2423

Discover Where Light Meets Digital at OFC2023

Join us from March 7 to 9, 2023 at OFC in San Diego, California, the world’s largest event for optical networking and communications.

Insights

December 9, 2022

Fit for Platform DSPs

Over the last two decades, power ratings for pluggable modules have increased as we moved…

Over the last two decades, power ratings for pluggable modules have increased as we moved from direct detection to more power-hungry coherent transmission: from 2W for SFP modules to 3.5 W for QSFP modules and now to 14W for QSSFP-DD and 21.1W for OSFP form factors. Rockley Photonics researchers estimate that a future electronic switch filled with 800G modules would draw around 1 kW of power just for the optical modules.

Around 50% of a coherent transceiver’s power consumption goes into the digital signal processing (DSP) chip that also performs the functions of clock data recovery (CDR), optical-electrical gear-boxing, and lane switching. Scaling to higher bandwidths leads to even more losses and energy consumption from the DSP chip and its radiofrequency (RF) interconnects with the optical engine.

Figure 1: Normalized power breakdown of the internal blocks of a 400ZR pluggable module. Although this breakdown may vary a bit among different vendors, the authors find it to be generally true for various DSP-based modules, both IM-DD and coherent. Source: R. Nagarajan et al., IEEE JLT (2021)

One way to reduce transceiver power consumption requires designing DSPs that take advantage of the material platform of their optical engine. In this article, we will elaborate on what that means for the Indium Phosphide platform.

A Jack of All Trades but a Master of None

Transceiver developers often source their DSP, laser, and optical engine from different suppliers, so all these chips are designed separately from each other. This setup reduces the time to market and simplifies the research and design processes but comes with trade-offs in performance and power consumption.

In such cases, the DSP is like a Swiss army knife: a jack of all trades designed for different kinds of optical engines but a master of none. For example, current DSPs are designed to be agnostic to the material platform of the photonic integrated circuit (PIC) they are connected to, which can be Indium Phosphide (InP) or Silicon. Thus, they do not exploit the intrinsic advantages of these material platforms. Co-designing the DSP chip alongside the PIC can lead to a much better fit between these components.

Co-Designing with Indium Phosphide PICs for Power Efficiency

To illustrate the impact of co-designing PIC and DSP, let’s look at an example. A PIC and a standard platform-agnostic DSP typically operate with signals of differing intensities, so they need some RF analog electronic components to “talk” to each other. This signal power conversion overhead constitutes roughly 2-3 Watts or about 10-15% of transceiver power consumption.

Figure 2: Simplified diagram of the building blocks of a coherent transceiver in which the DSP drives the optical engine directly from its digital-to-analog converter (DAC). This setup can minimize the power conversion overhead of optical transceivers.

However, the modulator of an InP PIC can run at a lower voltage than a silicon modulator. If this InP PIC and the DSP are designed and optimized together instead of using a standard DSP, the PIC could be designed to run at a voltage compatible with the DSP’s signal output. This way, the optimized DSP could drive the PIC directly without needing the RF analog driver, doing away with most of the power conversion overhead we discussed previously.

Figure 3: Comparison between the drive power and power consumption of three different PIC + DSP pairings: standard DSP with a silicon PIC, standard DSP with an InP PIC, and an optimized DSP with an InP.

Additionally, the optimized DSP could also be programmed to do some additional signal conditioning that minimizes the nonlinear optical effects of the InP material, which can reduce noise and improve performance.

Taking Advantage of Active Components in the InP Platform

Russell Fuerst, EFFECT Photonics’ Vice-President of Digital Signal Processing, gave us an interesting insight about designing for the InP platform in a previous interview:

When we started doing coherent DSP designs for optical communication over a decade ago, we pulled many solutions from the RF wireless and satellite communications space into our initial designs. Still, we couldn’t bring all those solutions to the optical markets.

However, when you get more of the InP active components involved, some of those solutions can finally be brought over and utilized. They were not used before in our designs for silicon photonics because silicon is not an active medium and lacked the performance to exploit these advanced techniques.

For example, the fact that the DSP could control laser and modulator components on the InP can lead to some interesting manipulations of light signals. A DSP that can control these components directly could generate proprietary waveforms or use non-standard constellation and modulation schemes that can boost the performance of a coherent transceiver and increase the capacity of the link.

Takeaways

The biggest problem for DSP designers is still improving performance while reducing power use. This problem can be solved by finding ways to integrate the DSP more deeply with the InP platform, such as letting the DSP control the laser and modulator directly to develop new waveform shaping and modulation schemes. Because the InP platforms have active components, DSP designers can also import more solutions from the RF wireless space.

Tags: analog electronics, building blocks, coherent, dispersion compensation, DSP, energy efficiency, Intra DCI, Photonics, PON, power consumption, reach, simplified

How To Make a Photonic Integrated Circuit

Insights

December 1, 2022

How To Make a Photonic Integrated Circuit

Photonics is one of the enabling technologies of the future. Light is the fastest information…

Photonics is one of the enabling technologies of the future. Light is the fastest information carrier in the universe and can transmit this information while dissipating less heat and energy than electrical signals. Thus, photonics can dramatically increase the speed, reach, and flexibility of communication networks and cope with the ever-growing demand for more data. And it will do so at a lower energy cost, decreasing the Internet’s carbon footprint. Meanwhile, fast and efficient photonic signals have massive potential for sensing and imaging applications in medical devices, automotive LIDAR, agricultural and food diagnostics, and more.

Given its importance, we want to explain how photonic integrated circuits (PICs), the devices that enable all these applications, are made.

Designing a PIC

The process of designing a PIC should translate an initial application concept into a functioning photonics chip that can be manufactured. In a short course at the OFC 2018 conference, Wim Bogaerts from Ghent University summarized the typical PIC design process in the steps we will describe below.

Figure 1 Summary of the steps in a PIC design flow process

Concept and Specifications: We first have to define what goes into the chip. A chip architect normally spends time with the customer to understand what the customer wants to achieve with the chip and all the conditions and situations where the chip will be used. After these conversations, the chip application concept becomes a concrete set of specifications that are passed on to the team that will design the internals of the chip. These specs will set the performance targets of the PIC design.
Design Function: Having defined the specs, the design team will develop a schematic circuit diagram that captures the function of the PIC. This diagram is separated into several functional blocks: some of them might already exist, and some of them might have to be built. These blocks include lasers, modulators, detectors, and other components that can manipulate light in one way or another.
Design Simulation: Making a chip costs a lot of money and time. With such risks, a fundamental element of chip design is to accurately predict the chip’s behavior after it is manufactured. The functional blocks are placed together, and their behavior is simulated using various physical models and simulation tools. The design team often uses a few different simulation approaches to reduce the risk of failure after manufacturing.
Design Layout: Now, the design team must translate the functional chip schematic into a proper design layout that can be manufactured. The layout consists of layers, component positions, and geometric shapes that represent the actual manufacturing steps. The team uses software that translates these functions into the geometric patterns to be manufactured, with human input required for the trickiest placement and geometry decisions.
Check Design Rules: Every chip fabrication facility will have its own set of manufacturing rules. In this step, the design team verifies that the layout agrees with these rules.
Verify Design Function: This is a final check to ensure that the layout actually performs as was originally intended in the original circuit schematic. The layout process usually leads to new component placement and parasitic effects that were not considered in the original circuit schematic. These tests might require the design team to revisit previous functional or layout schematic steps.

The Many Steps of Fabricating a PIC

Manufacturing semiconductor chips for photonics and electronics is one of the most complex procedures in the world. For example, back in his university days, EFFECT Photonics President Boudewijn Docter described a fabrication process with a total of 243 steps!

Yuqing Jiao, Associate Professor at the Eindhoven University of Technology (TU/e), explains the fabrication process in a few basic, simplified steps:

Grow or deposit your chip material
Print a pattern on the material
Etch the printed pattern into your material
Do some cleaning and extra surface preparation
Go back to step 1 and repeat as needed

Real life is, of course, a lot more complicated and will require cycling through these steps tens of times, leading to processes with more than 200 total steps. Let’s go through these basic steps in a bit more detail.

Figure 2 Basic steps of a semiconductor fabrication process that are repeated in a single fabrication cycle. An entire wafer manufacturing process requires tens of these cycles.

Layer Epitaxy and Deposition: Different chip elements require different semiconductor material layers. These layers can be grown on the semiconductor wafer via a process called epitaxy or deposited via other methods (which are summarized in this article).

Figure 3: Simplified example of PIC elements and the different material layers they require. Source: Smit et al. (2014)

Lithography (i.e. printing): There are a few lithography methods, but the one used for high-volume chip fabrication is projection optical lithography. The semiconductor wafer is coated with a photosensitive polymer film called a photoresist. Meanwhile, the design layout pattern is transferred to an opaque material called a mask. The optical lithography system projects the mask pattern onto the photoresist. The exposed photoresist is then developed (like photographic film) to complete the pattern printing.

Figure 4 Comparison of different optical lithography approaches. Contact and proximity printing keep the mask in contact with or close to the sample. Projection printing keeps the mask further away and is initially more expensive, but it is the technology of choice for high-volume manufacturing. Source: J. Shen, University of Waterloo PhD Thesis (2018)

Etching: Having “printed” the pattern on the photoresist, it is time to remove (or etch) parts of the semiconductor material to transfer the pattern from the resist into the wafer. There are several techniques that can be done to etch the material, which are summarized in this article.

Figure 5: Example of what a semiconductor wafer with resist (red color) on top of it looks like before and after an etching step.

Cleaning and Surface Preparation: After etching, a series of steps will clean and prepare the surface before the next cycle.
- Passivation: Adding layers of dielectric material (such a silica) to “passivate” the chip and make it more tolerant to environmental effects.
- Planarization: Making the surface flat in preparation of future lithography and etching steps.
- Metallization: Depositing metal components and films on the wafer. This might be done for future lithography and etching steps, or at the end to add electrical contacts to the chip.

Figure 6 summarizes how an InP photonic device looks after the steps of layer epitaxy, etching, dielectric deposition and planarization, and metallization.

Figure 6 Cross-section of a semiconductor wafer structure after: (a) epitaxial growth, (b) etching, (c) passivation and planarization, (d) metallization.

The Expensive Process of Testing and Packaging

Chip fabrication is a process with many sources of variability, and therefore much testing is required to make sure that the fabricated chip agrees with what was originally designed and simulated. Once that is certified and qualified, the process of packaging and assembling a device with the PIC follows.

While packaging, assembly, and testing are only a small part of the cost of electronic systems, the reverse happens with photonic systems. Researchers at the Technical University of Eindhoven (TU/e) estimate that for most Indium Phosphide (InP) photonics devices, the cost of packaging, assembly, and testing can reach around 80% of the total module cost. There are many research efforts in motion to reduce these costs, which you can learn more about in one of our previous articles.

Figure 7. Process cost breakdown of an InP PIC-based module as a percentage of the overall cost of manufacturing. Source: Latkowski et al., 2019

Especially after the first fabrication run of a new chip, there will be a few rounds of characterization, validation and revisions to make sure the chip performs up to spec. After this first round of characterization and validation, the chip must be made ready for mass production, which requires a series of reliability tests in several environmental different conditions. You can learn more about this process in our previous article on industrial hardening. For example, different applications need different certification of the temperatures in which the chip must operate in.

Temperature Standard	Temperature Range (°C)
Temperature Standard	Min	Max
Commercial (C-temp)	0	70
Extended (E-temp)	-20	85
Industrial (I-temp)	-40	85
Automotive / Full Military	-40	125

Table 1: Comparing the temperature ranges of different temperature hardening standards, including industrial and automotive/full military applications

Takeaways

The process of making photonic integrated circuits is incredibly long and complex, and the steps we described in this article are a mere simplification of the entire process. It requires tremendous amount of knowledge in chip design, fabrication, and testing from experts in different fields all around the world. EFFECT Photonics was founded by people who fabricated these chips themselves, understand the process intimately, and developed the connections and network to develop cutting-edge PICs at scale.

Tags: building blocks, c-temp, coherent, die testing, DSP, electron beam lithography, faults, I-temp, imprint lithography, InP, interfaces, optical lithography, reach, scale, wafer testing

What are FEC and PCS, and Why do They Matter

Insights

November 16, 2022

What are FEC and PCS, and Why do They Matter?

Coherent transmission has become a fundamental component of optical networks to address situations where direct…

Coherent transmission has become a fundamental component of optical networks to address situations where direct detect technology cannot provide the required capacity and reach.

While Direct Detect transmission only uses the amplitude of the light signal, Coherent optical transmission manipulates three different light properties: amplitude, phase, and polarization. These additional degrees of modulation allow for faster optical signals without compromising the transmission distance. Furthermore, coherent technology enables capacity upgrades without replacing the expensive physical fiber infrastructure on the ground.

However, the demand for data never ceases, and with it, developers of digital signal processors (DSPs) have had to figure out ways to improve the efficiency of coherent transmission. In this article, we will briefly describe the impact of two algorithms that DSP developers use to make coherent transmission more efficient: Forward Error Correction (FEC) and Probabilistic Constellation Shaping (PCS).

What is Forward Error Correction?

Forward Error Correction (FEC) implemented by DSPs has become a vital component of coherent communication systems. FEC makes the coherent link much more tolerant to noise than a direct detect system and enables much longer reach and higher capacity. Thanks to FEC, coherent links can handle bit error rates that are literally a million times higher than a typical direct detect link.

Let’s provide a high-level overview of how FEC works. An FEC encoder adds a series of redundant bits (called overhead) to the transmitted data stream. The receiver can use this overhead to check for errors without asking the transmitter to resend the data.

Figure 1 Simplified diagram of a network link with Forward Error Correction (FEC).

In other words, FEC algorithms allow the DSP to enhance the link performance without changing the hardware. This enhancement is analogous to imaging cameras: image processing algorithms allow the lenses inside your phone camera to produce a higher-quality image.

We must highlight that FEC is a block of an electronic DSP engine with its own specialized circuitry and algorithms, so it is a separate piece of intellectual property. Therefore, developing the entire DSP electronic engine (see Figure 2 for the critical component blocks of a DSP) requires ownership or access to specific FEC intellectual property.

Figure 2 Layout of the electronic engine used in a coherent optical transceiver, including the sequence the signal follows when processed by the engine.

What is Probabilistic Constellation Shaping?

DSP developers can transmit more data by transmitting more states in their quadrature-amplitude modulation process. The simplest kind of QAM (4-QAM) uses four different states (usually called constellation points), combining two different intensity levels and two different phases of light.

By using more intensity levels and phases, more bits can be transmitted in one go. State-of-the-art commercially available 400ZR transceivers typically use 16-QAM, with sixteen different constellation points that arise from combining four different intensity levels and four phases. However, this increased transmission capacity comes at a price: a signal with more modulation orders is more susceptible to noise and distortions. That’s why these transceivers can transmit 400Gbps over 100km but not over 1000km.

One of the most remarkable recent advances in DSPs to increase the reach of light signals is Probabilistic Constellation Shaping (PCS). In the typical 16-QAM modulation used in coherent transceivers, each constellation point has the same probability of being used. This is inefficient since the outer constellation points that require more power have the same probability as the inner constellation points that require lower power.

Figure 3: Comparison of conventional 16-QAM and a 16-QAM that uses Probabilistic Constellation Shaping (PCS). Diagram inspired by a figure from Infinera.

PCS uses the low-power inner constellation points more frequently and the outer constellation points less frequently, as shown in Figure 3. This feature provides many benefits, including improved tolerance to distortions and easier system optimization to specific bit transmission requirements. If you want to know more about it, please read the explainers here and here.

The Importance of Standardization and Reconfigurability

Algorithms like FEC and PCS have usually been proprietary technologies. Equipment and component manufacturers closely guarded their algorithms because they provided a critical competitive advantage. However, this often meant that coherent transceivers from different vendors could not operate with each other, and a single vendor had to be used for the entire network deployment.

Over time, coherent transceivers have increasingly needed to become interoperable, leading to some standardization in these algorithms. For example, the 400ZR standard for data center interconnects uses a public algorithm called concatenated FEC (CFEC). In contrast, some 400ZR+ MSA standards use open FEC (oFEC), which provides a more extended reach at the cost of a bit more bandwidth and energy consumption. For the longest possible link lengths (500+ kilometers), proprietary FECs become necessary for 400G transmission. Still, at least the public FEC standards have achieved interoperability for a large segment of the 400G transceiver market. Perhaps in the future, this could happen with PCS methods.

Future DSPs could switch among different algorithms and methods to adapt to network performance and use cases. For example, let’s look at the case of upgrading a long metro link of 650km running at 100 Gbps with open FEC. The operator needs to increase that link capacity to 400 Gbps, but open FEC could struggle to provide the necessary link performance. However, if the DSP can be reconfigured to use a proprietary FEC standard, the transceiver will be able to handle this upgraded link. Similarly, longer reach could be achieved if the DSP activates its PCS feature.

	400 ZR	Open ZR+	Proprietary Long Haul
Target Application	Edge data center interconnect	Metro, Regional data center interconnect	Long-Haul Carrier
Target Reach @ 400G	120km	500km	1000 km
Form Factor	QSFP-DD/OSFP	QSFP-DD/OSFP	QSFP-DD/OSFP
FEC	CFEC	oFEC	Proprietary
Standards / MSA	OIF	OpenZR+ MSA	Proprietary

Table 1: Summary of different use cases and standards for a 400G pluggable transceiver.

Takeaways

The entire field of communication technology can arguably be summarized with a single question: how can we transmit more information into a single frequency-limited signal over the longest possible distance?

DSP developers have many tools to answer this question, and two of them are FEC and PCS. Both technologies make coherent links much more tolerant of noise and can extend their reach. Future pluggables that handle different use cases must use different coding, error coding, and modulation schemes to adapt to different network requirements.

There are still many challenges ahead to improve DSPs and make them transmit even more bits in more energy-efficient ways. Now that EFFECT Photonics has incorporated talent and intellectual property from Viasat’s Coherent DSP team, we hope to contribute to this ongoing research and development and make transceivers faster and more sustainable than ever.

Tags: coherent, constellation shaping, DSP, DSPs, error compensation, FEC, PCS, power, Proprietary, reach, reconfigurable, standardized, standards

The Light Path to a Coherent Cloud Edge Banner

Insights

November 8, 2022

Improving Edge Computing with Coherent Optical Systems on Chip

Smaller data centers placed locally have the potential to minimize latency, overcome inconsistent connections, and…

Smaller data centers placed locally have the potential to minimize latency, overcome inconsistent connections, and store and compute data closer to the end-user. These benefits are causing the global market for edge data centers to explode, with PWC predicting that it will nearly triple from $4 billion in 2017 to $13.5 billion in 2024. Cloud-native applications are driving the construction of edge infrastructure and services. However, they cannot distribute their processing capabilities without considerable investments in real estate, infrastructure deployment, and management.

This situation leads to hyperscalers cooperating with telecom operators to install their servers in the existing carrier infrastructure. For example, Amazon Web Services (AWS) is implementing edge technology in carrier networks and company premises (e.g., AWS Wavelength, AWS Outposts). Google and Microsoft have strategies and products that are very similar. In this context, edge computing poses a few problems for telecom providers too. They must manage hundreds or thousands of new nodes that will be hard to control and maintain.

At EFFECT Photonics, we believe that coherent pluggables with an optical System-on-Chip (SoC) can become vital in addressing these datacom and telecom sector needs and enabling a new generation of distributed data center architectures. Combining the optical SoCs with reconfigurable DSPs and modern network orchestration and automation software will be a key to deploying edge data centers.

Edge data centers are a performance and sustainability imperative

Various trends are driving the rise of the edge cloud:

5G technology and the Internet of Things (IoT): These mobile networks and sensor networks need low-cost computing resources closer to the user to reduce latency and better manage the higher density of connections and data.
Content delivery networks (CDNs): The popularity of CDN services continues to grow, and most web traffic today is served through CDNs, especially for major sites like Facebook, Netflix, and Amazon. By using content delivery servers that are more geographically distributed and closer to the edge and the end user, websites can reduce latency, load times, and bandwidth costs as well as increasing content availability and redundancy.
Software-defined networks (SDN) and Network function virtualization (NFV). The increased use of SDNs and NFV requires more cloud software processing.
Augment and virtual reality applications (AR/VR): Edge data centers can reduce the streaming latency and improve the performance of AR/VR applications.

Several of these applications require lower latencies than before, and centralized cloud computing cannot deliver those data packets quickly enough. As shown in Table 1, a data center on a town or suburb aggregation point could halve the latency compared to a centralized hyperscale data center. Enterprises with their own data center on-premises can reduce latencies by 12 to 30 times compared to hyperscale data centers.

Type of Edge		Data center	Location	Number of DCs per 10M people	Average Latency	Size
On-premises edge		Enterprise site	Businesses	NA	2-5 ms	1 rack max
Network (Mobile)	Tower edge	Tower	Nationwide	3000	10 ms	2 rack max
	Outer edge	Aggrega- tion points	Town	150	30 ms	2-6 rack max
	Inner edge	Core	Major city	10	40 ms	10+ rack max
Regional edge		Regional	Major city	100	50 ms	100+ racks
Not edge		Hyperscale	State/ national	1	60+ ms	5000+ racks

Table 1: Types of edge data centers and their characteristics. Source: STL Partners

Cisco estimates that 85 zettabytes of useful raw data were created in 2021, but only 21 zettabytes were stored and processed in data centers. Edge data centers can help close this gap. For example, industries or cities can use edge data centers to aggregate all the data from their sensors. Instead of sending all this raw sensor data to the core cloud, the edge cloud can process it locally and turn it into a handful of performance indicators. The edge cloud can then relay these indicators to the core, which requires a much lower bandwidth than sending the raw data.

Figure 1 Global data center traffic vs. useable data created per year. Graphic sourced from Cisco Global Cloud Index.

Edge data centers therefore allow more sensor data to be aggregated and processed to make systems worldwide smarter and more efficient. The ultimate goal is to create entire “smart cities” that use this sensor data to benefit their inhabitants, businesses, and the environment. Everything from transport networks to water supply and lightning could be improved if we have more sensor data available in the cloud to optimize these processes. Distributing data centers is also vital for future data center architectures. While centralizing processing in hyper-scale data centers made them more energy-efficient, the power grid often limits the potential location of new hyperscale data centers. Thus, the industry may have to take a few steps back and decentralize data processing capacity to cope with the strain of data center clusters on power grids. For example, data centers can be relocated to areas where spare power capacity is available, preferably from nearby renewable energy sources. EFFECT Photonics envisions a system of datacentres with branches in different geographical areas, where data storage and processing are assigned based on local and temporal availability of renewable (wind-, solar-) energy and total energy demand in the area.

Figure 2: High-speed fiber-optic connections allow data processing and storage to move to locations where excess (green) energy is available. If power is needed for other purposes, such as charging electric vehicles, data can be moved elsewhere

Coherent technology simplifies the scaling of edge data center interconnects

As edge data center interconnects became more common, the issue of how to interconnect them became more prominent. Direct detect technology had been the standard in the short-reach data center interconnects. However, reaching the distances greater than 50km and bandwidths over 100Gbps required for modern edge data center interconnects required external amplifiers and dispersion compensators that increased the complexity of network operations. At the same time, advances in electronic and photonic integration allowed longer reach coherent technology to be miniaturized into QSFP-DD and OSFP form factors. This progress allowed the Optical Internetworking Forum (OIF) to create the 400ZR and ZR+ standards for 400G DWDM pluggable modules. With small enough modules to pack a router faceplate densely, the datacom sector could profit from a 400ZR solution for high-capacity data center interconnects of up to 80km. If needed, extended reach 400ZR+ pluggables can cover several hundreds of kilometers. Cignal AI forecasts that 400ZR shipments will dominate in the edge applications, as shown in Figure 3.

Figure 3: Forecast of 100G port equivalents shipped for edge applications. These shipments are overwhelmingly 400ZR standard technology. Source: Cignal AI Transport Applications Report Q42021.

Further improvements in integration can further boost the reach and efficiency of coherent transceivers. For example, by integrating all photonic functions on a single chip, including lasers and optical amplifiers, EFFECT Photonics’ optical System-On-Chip (SoC) technology can achieve higher transmit power levels and longer distances while keeping the smaller QSFP-DD form factor, power consumption, and cost.

Maximizing Edge Computing with Automation

With the rise of edge data centers, telecom providers must manage hundreds or thousands of new nodes that will be hard to control and maintain. Furthermore, providers also need a flexible network with pay-as-you-go scalability that can handle future capacity needs. Fortunately, several new technologies are enabling this scalable and automated network management.

First of all, the rise of self-tuning algorithms has made the installation of new pluggables easier than ever. They eliminate additional installation tasks such as manual tuning and record verification. They are host-agnostic, can plug into any third-party host equipment, and scale as you grow. Standardization also allows modules from different vendors to communicate with each other, avoiding compatibility issues and simplifying upgrade choices. The communication channels used for self-tuning algorithms can also be used for remote diagnostics and management, such as the case of EFFECT Photonics NarroWave technology.

Automation potential improves further by combining artificial intelligence with the software-defined networks (SDNs) framework that virtualizes and centralizes network functions. This creates an automated and centralized management layer that can allocate resources efficiently and dynamically. For example, AI in network management will become a significant factor in reducing the energy consumption of future telecom networks.

Figure 2: Comparing a traditional network approach (left) with an SDN/NFC approach (right).

Future smart transceivers with reconfigurable digital signal processors (DSPs) can give the AI-controlled management layer even more degrees of freedom to optimize the network. These smart transceivers will relay more device information for diagnosis, and depending on the management layer instructions, they can change their coding schemes to adapt to different network requirements

Takeaways

Cloud-native applications require edge data centers with lower latency, and that better fit the existing power grid. However, their implementation came with the challenges of more data center interconnects and a massive increase in nodes to manage. Fortunately, coherent pluggables with self-tuning can play a vital role in addressing these datacom and telecom sector challenges and enabling a new generation of distributed data center architectures. Combining these pluggables with modern network orchestration and automation software will boost the deployment of edge data centers. EFFECT Photonics believes that with these automation technologies (self-tuning, SDNs, AI), we can reach the goal of a self-managed, zero-touch automated network that can handle the massive scale-up required for 5G networks and edge computing.

Tags: 400ZR, artificial intelligence, cloud, coherent, computing, data centers, DSP, edge, edge data centers, infrastructure, latency, network, network edge, operators, optical system-on-chip, pluggables, self-tuning, services

Sub-Assemblies: pITLA

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DSP

EFFECT Photonics to Become the Most Highly Vertically Integrated, Independent Coherent Optical Module Vendor

About EFFECT Photonics

About Viasat

Explore Our OFC2023 Demos:

A Jack of All Trades but a Master of None

Co-Designing with Indium Phosphide PICs for Power Efficiency

Taking Advantage of Active Components in the InP Platform

Takeaways

Designing a PIC

The Many Steps of Fabricating a PIC

The Expensive Process of Testing and Packaging

Takeaways

What is Forward Error Correction?

What is Probabilistic Constellation Shaping?

The Importance of Standardization and Reconfigurability

Takeaways

Edge data centers are a performance and sustainability imperative

Coherent technology simplifies the scaling of edge data center interconnects

Maximizing Edge Computing with Automation

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Sub-Assemblies: pITLA

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